#------------------------------
# set the top design
#------------------------------
set top_design "present_encryptor_top"
define_design_lib WORK -path ./analyzed/WORK

#------------------------------
# set the necessary path
#------------------------------
set src        .
set run        .
set log        .
set out        .

#-----------------------------
# set the source file and parition
#-----------------------------
lappend search_path  ${src}

#define_design_lib work -path ${work}

# If you have multiple files to be synthesized, such as you have a.v, b.v, c.v, and d.v,
# you can set sflist as follows
# set sflist {a b c d}
set sflist {key_update Permutation present_encryptor_top Sbox sub_per substition}

#-----------------------------
# read the RTL files
#-----------------------------
foreach module $sflist {
analyze -f verilog -lib work $module.v
}

elaborate ${top_design} > ${log}/${top_design}_elaborate.log

#-------------------------------------
# check the design with DW and gtech
#-------------------------------------
check_design > ${log}/${top_design}_pre_check.log

#--------------------------
# set the current design
#--------------------------
current_design ${top_design} 

#--------------------------
# link
#--------------------------
link
uniquify

#------------------------
# save the flat with DW and gtech
#------------------------
write_file -f verilog -hierarchy -output ${run}/${top_design}_unmapped.v
write_file -f ddc     -hierarchy -output ${run}/${top_design}_unmapped.ddc

